Electronic design automation (EDA) tools are used for designing, verifying, and implementing electronic systems and component circuits. Within an electronic system, hundreds of integrated circuits may be interconnected on one or more printed circuit boards (PCBs). Integrated circuits comprise an ever-increasing number of interconnected transistors to enable a set of intended functions.
In emulation systems, emulation chips may comprise hardware components, such as processors, capable of processor-based (e.g., hardware-based) emulation of logic systems, such as application specific integrated circuits (ASICs), to test their capabilities. A common method of hardware design verification is to use processor-based hardware emulators to emulate the design prior to physically manufacturing the integrated circuit(s) of the hardware. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels and instructions is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
Conventional hardware emulators are comprised of identical processors. The processors are generally arranged into groups of processors known as “clusters.” In a conventional hardware emulator, each processor performs an identical set of functions, such as retrieving data from a memory, evaluating the data, and writing the processed result back into either the same or different memory. Processors typically address the memory via an instruction word. The instruction word is stored in an instruction memory and contains a read address for the data to be evaluated and a Boolean function table that instructs the processor on how to evaluate the data. The processor then stores the produced result back to the same memory location as indicated by the instruction address.
Each processor of the processor-based emulation system is typically configured to operate in a lock step mode. During the lock step mode, every processor of the processor-based emulation architecture executes the same instruction number at the same time. In the currently utilized processor-based emulation architecture, a single chip may include thousands of processors, which means that there may be millions of processors, across hundreds of chips, each executing instructions at the same time. The synchronous execution by many, if not all, of the processors of a system and the static scheduling of instructions is not conducive to power regulation, because the system goes from idle (little to no power consumption) to maximum power consumption, in one execution step. Such an event in the system when the power consumption usage of the system goes from idle power to maximum power from one step to the next is called a “load step.”
The emulation system generally comprises measures for establishing a power delivery network to components of the system, such as processors. This power delivery network sometimes includes models for a voltage regulator module (VRM) that generates at least one predetermined supply voltage level. When large load steps occur in the emulation systems, for example, when the current goes from a low value to a high value, particularly in high-power applications, the VRM, power distribution conductors, and several different scales of capacitances of the emulation system are not able to compensate, and it becomes difficult to hold a constant voltage. For instance, the capacitance in the emulation chip attempts to hold voltage steady at the scale of frequencies above roughly 300 MHz, but is limited in value depending on how much charge the capacitance can supply. The capacitance on an emulation board reacts slowly because the capacitance effectiveness is limited by the inductance of pathways, which resist changes in the current at high frequencies. Also, there is generally not sufficient capacitance on the emulation chip and the emulation board to supply charge when the circuits of the system architecture go from a very low power to a very high power in a short amount of time. In an emulation system, constant voltage is required for optimal emulation chip function, since most of the switching in the emulation chip is synchronized and the behavior of the transistors cannot be analyzed when the voltage is not held at a pre-determined constant value or at least within a pre-determined range.
Conventional computing systems, such as emulation systems, overcome the voltage fluctuation problem with a VRM configured to regulate the voltage and keep the voltage value at a pre-determined constant value whenever there is a change in the voltage. In operation, the VRM continuously monitors the voltage and subsequently raises or lowers the voltage value to a target set point (or within a target range) when there is any deviation of voltage value from the target set point (or from the target range). For example, if the pre-determined voltage value is set in the emulation system, and the current is increased from a low value to a high value, an IR drop (voltage drop) may occur, which may result in increase or decrease of value of voltage, and thus the voltage may change from the target value. This change in voltage occurs because there is more voltage drop during transmission when more current is being drawn. Also, the voltage at the VRM has to be higher so that the voltage at the emulation chip remains at the pre-determined voltage value.
The IR drop is the voltage reduction that occurs in the power delivery networks in the emulation system. The IR drop may be static or dynamic, and typically results from an existence of non-ideal elements, such as, a resistance within the power and ground supply wiring, and the capacitance between them. There may be an IR drop of a chip package; there may also be a power distribution network inside the emulation chip that may experience some IR drop. The VRM in the system is configured to keep the pre-determined voltage value that has been programmed into the memory, or set by a reference feedback network, etc., of the VRM at a constant value, while taking into consideration the IR drops. In operation, while the current being drawn into the system is increased from a lower value to a higher value, the VRM is compensating the amount of voltage in the system, e.g., pushing out more power to keep the voltage value at a target level regardless of the change of load of the current. In some cases, during the period before the VRM actually adjusts the power, the emulation chip is also not operating, because, in such cases, the emulation chip is designed to function only when the voltage is within a certain range and the voltage at the transistors is below the specified voltage value. In some cases, when the voltage value is out of specification, the transistors do not switch as fast as desired, which may cause timing violations for switching of transistors and/or any number of logical errors.
FIG. 1 is a graphical diagram 100 illustrating the effect on the voltage during a load step in a prior-art emulation system. The graphical diagram 100 shows the voltage at a die of an emulation system, over a timescale where several emulation cycles were run. At a time near a trigger (towards a left-side of the graphical diagram 100), an ASIC goes from an idle state to running a sequence of high-power emulation cycles. As shown in FIG. 1, there is a voltage drop, and subsequently, over a period of time, the VRM adjusts the voltage back to a predetermined value or into a predetermined range. During the intervening period of the voltage drop, the voltage at the transistors is out of the specification, causing the transistors not to switch as quickly as desired. Slowed transistor performance causes timing violations, which, in turn, causes logical errors.
Therefore, there is a need for computing systems to be able to mitigate the load step and provide effective and efficient power management for electrical design emulation.